4+ day, 23+ min ago   (473+ words) By Guy Cortez, Dan Alexandrescu, and Aaron Barker The semiconductor industry has invested heavily in embedded monitors to gain visibility into advanced silicon. Those monitors are essential, but the next step is not simply to collect a larger volume of…...

4+ day, 23+ hour ago   (1623+ words) Google, Amazon, and now OpenAI have competitive offerings and are gaining share. GPUs are 70% of installed worldwide AI compute capacity by manufacturer (see figure 1), with custom silicon accounting for 30%, primarily Google and Amazon. Fig. 1: Current installed worldwide AI compute capacity…...

1+ week, 3+ day ago   (328+ words) In-Depth Reports and Deals New Technologies Security Vehicles Research Quantum Workforce | Education Events and Webinars EPFL researchers demonstrated a GaN-on-Si transistor using a polarization superjunction that sustained more than 3.4 kV, along with diodes that exceeded 3.9 kV. Seoul National University-led researchers…...

1+ week, 6+ day ago   (815+ words) Part I – Pioneering work in developing CFET-critical modules: an improved backside contact module and a novel gate stack for threshold voltage tuning. By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi The semiconductor industry is going through a major architectural transition,…...

2+ week, 1+ day ago   (180+ words) Researchers from Purdue University published a technical paper titled “Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era.” Abstract Excerpt: The paper presents a “cycle-level simulation framework” for modern GPU generations including Ampere, Hopper, and Blackwell. It…...

2+ week, 2+ day ago   (173+ words) Researchers from Georgia Institute of Technology published a technical paper titled “Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation.” Abstract Excerpt: The paper analyzes “wafer-scale optical interconnects” for mixture-of-experts LLM training…...

3+ week, 31+ min ago   (997+ words) Chips are getting bigger, more modular, and much more capable as new innovations mix with existing processes and long-researched projects go mainstream. Multi-die assemblies and heterogeneous integration are becoming standard in leading-edge servers and high-end edge devices, forcing broad changes…...

3+ week, 4+ day ago   (257+ words) Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators. SE: Compute clusters comprised of multiple processors acting as a single computer present many design challenges around…...

3+ week, 6+ day ago   (117+ words) 2D CFET scaling; PIM chiplet voltage-droop control; advanced-node layout repair; lithography defect prediction; 3D-IC failure analysis; chiplet and interposer optimization; 4H-SiC wafer slicing. The post Chip Industry Technical Paper Roundup: Aug. 18 appeared first on Semiconductor Engineering. Chip Industry Technical Paper Roundup:…...