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Deep insights into the increasingly complex task of designing, testing, integrating, and manufacturing semiconductors. Explore the latest in Semiengineering and cutting-edge chip technology.
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News
Modeling Predicts Cure And Thermal Endurance Of Advanced Packaging Underfill (NIST, UCSD et al.)
2+ day, 9+ hour ago (282+ words) Researchers at the NIST, UCSD et al. published a technical paper titled “Predicting Cure Evolution and Thermal Endurance of a Highly Filled Epoxy Underfill for Advanced Packaging.” Abstract Excerpt: “Epoxy underfill materials are critical to advanced semiconductor packaging by enhancing…...
Beyond Thickness: Using Picosecond Ultrasonic Technology For SiCr Process Control In BCD Devices
3+ day, 23+ hour ago (172+ words) By Huayuan Li, Alex Hong, Johnny Mu, and Timothy Kryman Building a bipolar-CMOS-DMOS (BCD) device is one challenge; maintaining the material consistency required for reliable high-volume manufacturing (HVM) is another. In fact, achieving consistent device performance starts long before the…...
Smart Outlier Detection
5+ day, 23+ hour ago (130+ words) Just because a chip is deemed good doesn't mean it will work as expected. The post Smart Outlier Detection appeared first on Semiconductor Engineering. Nearly all leading-edge designs today are multi-die assemblies, which means that one defective die can render…...
Chip Industry Week In Review
1+ week, 2+ day ago (328+ words) In-Depth Reports and Deals New Technologies Security Vehicles Research Quantum Workforce | Education Events and Webinars EPFL researchers demonstrated a GaN-on-Si transistor using a polarization superjunction that sustained more than 3.4 kV, along with diodes that exceeded 3.9 kV. Seoul National University-led researchers…...
Multi-Die Design for Automotive Applications
1+ week, 4+ day ago (178+ words) Multi-die design is becoming indispensable for automotive applications, such as ADAS and IVI, addressing demands for reliability and safety. The post Multi-Die Design for Automotive Applications appeared first on Semiconductor Engineering. Electronics for automobiles sit in the middle of two…...
Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations
1+ week, 5+ day ago (815+ words) Part I – Pioneering work in developing CFET-critical modules: an improved backside contact module and a novel gate stack for threshold voltage tuning. By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi The semiconductor industry is going through a major architectural transition,…...
Trust, But Verify
1+ week, 6+ day ago (274+ words) We trust designers to do the best they can, but know they cannot be perfect. That’s why we verify. When AI gets involved, it cannot be trusted. Long before it became an English proverb, it was being used in practice,…...
Cycle-Level Simulator for Distributed GPUs For AI Workloads (Purdue)
2+ week, 23+ hour ago (180+ words) Researchers from Purdue University published a technical paper titled “Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era.” Abstract Excerpt: The paper presents a “cycle-level simulation framework” for modern GPU generations including Ampere, Hopper, and Blackwell. It…...
Programmable Silicon Photonics Filter Enables Continuous Laser Wavelength Tuning (UiT, Stanford)
2+ week, 23+ hour ago (104+ words) Researchers at UiT The Arctic University of Norway and Stanford University published a technical paper titled “Intracavity Laser Wavelength Tuning by a Programmable Forward-Only Silicon Photonics Interferometer Mesh.” Abstract Excerpt: “We exploit a recently proposed concept for a programmable, mechanically…...
Generative Design Optimizes Liquid-Cooling Channels For 2.5D And 3D Packages (UM-Dearborn)
2+ week, 2+ day ago (186+ words) Researchers from University of Michigan-Dearborn published a technical paper titled “Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging.” Abstract Excerpt: The paper presents “a physics-guided generative design framework for liquid cooling channel topology optimization” in…...