4+ day, 7+ hour ago   (591+ words) Discrete steps are being merged with others as dimensions shrink into the angstrom range. The lines between discrete semiconductor manufacturing processes are starting to blur at sub-2nm nodes as transistors continue to shrink, sensitivity to various processes rises, and the…...

6+ day, 7+ hour ago   (109+ words) HBF for LLM inference; M3D SRAM with BEOL pass-gates at 2nm; distributed GPU architectures; hybrid HBM-HBF memory; GaN-on-silicon polarization superjunctions; programmable silicon photonics; Al dopant activation in 4H-SiC. The post Chip Industry Technical Paper Roundup: Sept. 8 appeared first on Semiconductor Engineering. Chip…...

1+ week, 3+ day ago   (328+ words) In-Depth Reports and Deals New Technologies Security Vehicles Research Quantum Workforce | Education Events and Webinars EPFL researchers demonstrated a GaN-on-Si transistor using a polarization superjunction that sustained more than 3.4 kV, along with diodes that exceeded 3.9 kV. Seoul National University-led researchers…...

1+ week, 4+ day ago   (553+ words) Robots and autonomous vehicles are both edge devices, but a humanoid has wheels as well as fingers. Close interaction with humans raises the stakes. The market for robots and humanoids is growing rapidly for industrial applications, but it’s poised for…...

1+ week, 5+ day ago   (541+ words) SE: Does the industry have a good understanding of the impact of AI on PQC? SE: How soon? Shouldn’t it have already happened? Petr: Assuming there are people in that stack who can do that. Giles: I completely agree. It…...

1+ week, 6+ day ago   (98+ words) Semiconductor Engineering Chip Industry Technical Paper Roundup: Sep. 1 Wafer-scale optical interconnects for LLM training; Rowhammer-based inference attacks; 3D-IC test cases; liquid cooling for 2.5D/3D packages; wafer-scale 2D semi growth; DL-based parameter extraction for 2D transistors; and chip-placement optimization. New technical papers recently added…...

1+ week, 6+ day ago   (815+ words) Part I – Pioneering work in developing CFET-critical modules: an improved backside contact module and a novel gate stack for threshold voltage tuning. By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi The semiconductor industry is going through a major architectural transition,…...

2+ week, 1+ day ago   (207+ words) Researchers from Georgia Institute of Technology and Synopsys published a technical paper titled “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.” Abstract Excerpt: The paper proposes “a monolithic-3D (M3D) 6T SRAM at the 2nm node” that integrates BEOL…...

2+ week, 4+ day ago   (159+ words) Advanced-node design to reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs. How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes Advanced-node design to reduce iterations and improve correlation for DTCO-focused advanced AI and…...