3+ hour, 18+ min ago (751+ words) Growing use cases include life science AI, reducing memory and I/O bottlenecks, data prepping, wireless networking, and as insurance for evolving protocols. FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can improve the flow of data. Nevertheless, the market for FPGAs is expanding. New application areas include: One evolving area is robotics, which require deterministic latency and real-time decision-making on the edge using heterogeneous data from cameras and sensors. "It could be voice, video, whatever " things that you need sensor fusion," said Yadavalli. In today's fast-changing, highly connected, and AI-enabled landscape, there's no single answer about whether designers should use FPGAs, ASICs, or another type of IC. Evolving algorithms AI/ML models are a moving target, and while FPGAs can be reprogrammed…...

12+ hour, 39+ min ago (305+ words) A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. Abstract "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration.... " read more The post Leveraging NEMS To Address Critical Hardware Security Challenges In Advanced Packaging (U. of Florida) appeared first on Semiconductor Engineering. A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration. This paper presents Nanoelectromechanical Systems (NEMS) as an emerging…...

3+ hour, 22+ min ago (266+ words) Bringing logic, memory, and accelerators into tight physical proximity. Vertical stacking takes integration further by physically aligning these dies in three dimensions. Memory or accelerators can be placed directly above compute tiles, dramatically reducing interconnect distances. The result is higher bandwidth, lower latency, and lower energy per bit'key benefits for data-intensive applications. Together, chiplets and vertical stacking form the foundation of today's scalable multi-die systems. The integration of 3D-IC technology depends on a set of advanced interconnect and packaging technologies that define how dies communicate and share power. Each of these technologies supports different density, performance, and cost goals. TSVs enable true 3D stacking, interposers facilitate chiplet assemblies, and hybrid bonding delivers the highest interconnect density available today. These factors are crucial to achieving performance, reliability, and yield goals at the production scale. As data-intensive workloads demand higher bandwidth and tighter…...

3+ hour, 20+ min ago (620+ words) Designing resilient chips with SLM can help combat aging effects, security threats, and get to market faster with higher yields. Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, understanding the full lifecycle can enable chip designs that are more resilient to aging effects and new security threats, with the ability to monitor and potentially mitigate issues after deployment. While the benefits of SLM are clear, integrating these capabilities into chip designs introduces new complexities and considerations that must be addressed throughout the development process. This leads to important questions about how SLM strategies should…...

11+ hour, 46+ min ago (319+ words) A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed... " read more The post On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien) appeared first on Semiconductor Engineering. A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as…...