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external laser source Archives
9+ hour, 49+ min ago (81+ words) Semiconductor Engineering tag: external laser source CPO Will Dominate Scale-Up: Link Budgets For d B And $ Are Key Flash Getting Stacked High-Bandwidth Version AI Accelerator Testing Depends On DFT Innovations Chiplets Need A New Workflow HBM Shifts Testing Left To…...
Building Multi-Agent Systems For ASIC Flows
10+ hour, 9+ min ago (132+ words) How agents can be used to divide and conquer IC design problems. The post Building Multi-Agent Systems For ASIC Flows appeared first on Semiconductor Engineering. If one AI agent can solve a problem in a certain amount of time, can…...
PCIe Benefits From AI, Despite Scaling Protocols
10+ hour, 22+ min ago (1790+ words) CXL is also gaining traction in AI processing, while MIPI and others are growing at the edge. CXL is closely related to PCIe and lies atop the PCIe stack. It's had a slow start as developers evaluate its utility, and…...
CPO Will Dominate Scale-Up: Link Budgets For d B And $ Are Key
10+ hour, 24+ min ago (1554+ words) Optical interconnects are needed to boost GPU throughput and utilization. Fig. 1: A demo compute rack with 100% CPO interconnect. Source: Ayar Labs and Wiwynn The other link budget is monetary. All of the components in the link must cost less in…...
High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited So Cs
1+ day, 10+ hour ago (142+ words) By Ash Patel and Shubharthi Datta, Synopsys, and Chuanyun Fan, Cisco After successful simulation and tape-out, the team prepared for the arrival of silicon. This included setting up the Advantest Link Scale hardware and software, designing the ATE board and…...
Why Analog And Mixed-Signal Chips Resist Adaptive Test
1+ day, 10+ hour ago (1451+ words) Analog behavior is difficult to compress into simple pass/fail decisions that could reduce redundant coverage. Analog and mixed-signal test has reached an important turning point. While a new standard enables engineers to quantify test coverage of these essential devices…...
2026 ASMC " Building the Core Pillars for AI in Semiconductors
1+ day, 10+ hour ago (211+ words) A roadmap for operationalizing AI at scale and achieving sustained competitive advantage across the semiconductor lifecycle. The post 2026 ASMC " Building the Core Pillars for AI in Semiconductors appeared first on Semiconductor Engineering. Abstract: This presentation outlines a practical pathway for…...
Advancements in Corona Noncontact Metrology Tools, Cn CV, for Industrial WBG Wafer Testing and Electrical Defect Related Yield Prediction
1+ day, 10+ hour ago (188+ words) Metrology for defect screening, yield learning, and process control in WBG manufacturing. The post Advancements in Corona Noncontact Metrology Tools, Cn CV, for Industrial WBG Wafer Testing and Electrical Defect Related Yield Prediction appeared first on Semiconductor Engineering. In this…...
Co-Packaged Optics Testing Faces Steep Data Center Ramp
1+ day, 10+ hour ago (524+ words) Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods for electrical and optical testing. The CPO product profile, just in terms of optical engine count and connector differences, adds…...
Test Anything, Anywhere, Anytime
1+ day, 10+ hour ago (323+ words) In-field testing is essential for quickly detecting emerging defects throughout a device's operational lifespan. In environments such as data centers or automotive systems, where reliability is critical, the ability to periodically test devices in the field is essential for ensuring…...