Please confirm you are human

This browser or connection looks automated. Press and continuously hold the control for 3 seconds to enable Google-hosted web results and, when separately allowed, AI-assisted answers.

A successful check enables 100 search requests. Interactive access does not authorize scraping, systematic collection, or reuse of search output.

Hold with a pointer, or hold Space or Enter.

News

Semiconductor Engineering
semiengineering.com > modular-verification-of-rtl-processors-against-isa-contracts-mit-google-uw

Modular Verification of RTL Processors Against ISA Contracts (MIT, Google, UW)

2+ hour, 19+ min ago   (212+ words) Researchers from MIT, Google, and University of Washington published a technical paper titled “Granite: A Modular Methodology for Foundational Verification of Hardware-Software Leakage Contracts.” Abstract Excerpt: “Granite is a methodology for modular verification of both functional correctness and nonleakage of…...

Semiconductor Engineering
semiengineering.com > chip-industry-week-in-review-149

Chip Industry Week In Review

2+ day, 14+ hour ago   (438+ words) DAC’s big buzz; CHIPS Act $; China’s immersion DUV; UMC expands; SIA’s state of the industry; DRAM shortages; earnings; PCB design credential program; IBM’s quantum advantage; AI security alliance; foreign robotics ban. The energy and buzz at this year’s Design Automation…...

Semiconductor Engineering
semiengineering.com > 2d-p-type-semiconductors-with-oxide-n-channel-transistors-for-complementary-beol-cmos-stanford-hanyang

2D P-Type Semiconductors with Oxide N-Channel Transistors For Complementary BEOL CMOS (Stanford, Hanyang)

3+ day, 22+ hour ago   (117+ words) Researchers from Stanford University and Hanyang University published a technical paper titled “Bridging the p-type gap in oxide electronics with 2D semiconductors.” “The review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle…...

Semiconductor Engineering
semiengineering.com > deployable-3d-structures-from-wafer-fabricated-precursors-u-of-houston-toyota-imperial-college-london

Deployable 3D Structures from Wafer-Fabricated Precursors (U. of Houston, Toyota, Imperial College London)

3+ day, 22+ hour ago   (150+ words) Researchers from University of Houston, Toyota, and Imperial College London published a technical paper titled “Deployable 3D Architectures from Wafer-Fabricated Precursors.” The paper shows that “standard wafer fabrication can produce free-standing, mechanically stable, doubly-curved 3D structures with prescribed Gaussian curvature — a capability…...

Semiconductor Engineering
semiengineering.com > chip-industry-technical-paper-roundup-july-28

Chip Industry Technical Paper Roundup: July 28

5+ day, 14+ hour ago   (206+ words) HW methods to throttle AI; M3D DRAM; interconnect signal-integrity analysis; 3D mask effects in high/hyper-NA EUV litho; compute-in-interconnect and memory; NbAs nanowire interconnects; and 3D conformal thin-film patterning. The post Chip Industry Technical Paper Roundup: July 28 appeared first on Semiconductor Engineering. New…...

Semiconductor Engineering
semiengineering.com > research-bits-july-28

Research Bits: July 28

5+ day, 14+ hour ago   (199+ words) The device structure evolves through successive iterations of the computational optimization process, resulting in irregular patterns of holes and ridges. “Inverse design becomes practical when fabrication realities are built into the optimization,” said Kiyoul Yang, assistant professor of electrical engineering…...

Semiconductor Engineering
semiengineering.com > preparing-for-ai-driven-chip-design-and-verification

Preparing For AI-Driven Chip Design And Verification

6+ day, 14+ hour ago   (468+ words) Jobs, markets, and economics are undergoing dramatic changes, but it’s still too early to know how this will all shake out. SE: How will AI affect engineering jobs? SE: Is the learning curve changing with AI? SE: How do we…...

Semiconductor Engineering
semiengineering.com > ai-agent-orchestration-for-asic-autonomy

AI Agent Orchestration For ASIC Autonomy

6+ day, 14+ hour ago   (127+ words) How to achieve a 10X productivity improvement using AI agents. The post AI Agent Orchestration For ASIC Autonomy appeared first on Semiconductor Engineering. The use of AI agents in chip design has been limited to small portions of the design flow…...

Semiconductor Engineering
semiengineering.com > why-the-semiconductor-industry-needs-a-common-language-for-functional-safety

Why the Semiconductor Industry Needs A Common Language For Functional Safety

6+ day, 14+ hour ago   (328+ words) A standardized way for future automation. As designs become more complex and supply chains more distributed, these challenges only continue to grow. The industry has long benefited from standards that define what is required to achieve functional safety. Standards such…...

Semiconductor Engineering
semiengineering.com > the-impact-of-ai-automation-on-chip-design

The Impact Of AI Automation On Chip Design

1+ week, 3+ day ago   (242+ words) Change is coming, but how quickly depends on the availability of data and when chipmakers are confident enough to let AI take over. Agentic solutions are more than a wrapper on top of existing tools. They will transform tools into…...