1+ hour, 56+ min ago (751+ words) Growing use cases include life science AI, reducing memory and I/O bottlenecks, data prepping, wireless networking, and as insurance for evolving protocols. FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can improve the flow of data. Nevertheless, the market for FPGAs is expanding. New application areas include: One evolving area is robotics, which require deterministic latency and real-time decision-making on the edge using heterogeneous data from cameras and sensors. "It could be voice, video, whatever " things that you need sensor fusion," said Yadavalli. In today's fast-changing, highly connected, and AI-enabled landscape, there's no single answer about whether designers should use FPGAs, ASICs, or another type of IC. Evolving algorithms AI/ML models are a moving target, and while FPGAs can be reprogrammed…...

1+ hour, 59+ min ago (620+ words) Designing resilient chips with SLM can help combat aging effects, security threats, and get to market faster with higher yields. Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, understanding the full lifecycle can enable chip designs that are more resilient to aging effects and new security threats, with the ability to monitor and potentially mitigate issues after deployment. While the benefits of SLM are clear, integrating these capabilities into chip designs introduces new complexities and considerations that must be addressed throughout the development process. This leads to important questions about how SLM strategies should…...

2+ hour, 1+ min ago (266+ words) Bringing logic, memory, and accelerators into tight physical proximity. Vertical stacking takes integration further by physically aligning these dies in three dimensions. Memory or accelerators can be placed directly above compute tiles, dramatically reducing interconnect distances. The result is higher bandwidth, lower latency, and lower energy per bit'key benefits for data-intensive applications. Together, chiplets and vertical stacking form the foundation of today's scalable multi-die systems. The integration of 3D-IC technology depends on a set of advanced interconnect and packaging technologies that define how dies communicate and share power. Each of these technologies supports different density, performance, and cost goals. TSVs enable true 3D stacking, interposers facilitate chiplet assemblies, and hybrid bonding delivers the highest interconnect density available today. These factors are crucial to achieving performance, reliability, and yield goals at the production scale. As data-intensive workloads demand higher bandwidth and tighter…...

10+ hour, 25+ min ago (319+ words) A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed... " read more The post On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien) appeared first on Semiconductor Engineering. A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as…...

11+ hour, 18+ min ago (305+ words) A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. Abstract "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration.... " read more The post Leveraging NEMS To Address Critical Hardware Security Challenges In Advanced Packaging (U. of Florida) appeared first on Semiconductor Engineering. A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration. This paper presents Nanoelectromechanical Systems (NEMS) as an emerging…...

1+ day, 2+ hour ago (368+ words) Given the importance of power to many chip designs, it is amazing how few tools take power seriously. For quite some time I have felt that the way the industry approaches power is less than optimal. Techniques such as clock gating and power gating have been used to reduce the amount of unnecessary activity and leakage, but is there more activity that does not contribute to an intended action? About a decade ago, EDA companies and standards bodies attempted to create a new verification methodology that would start from the target goals of a device and work out how to make that happen in the design. This effort was called Portable Stimulus " a name whose historical context was dubious, and which only adds to the confusion about what it can do. But the semiconductor industry does not like change, and…...

4+ day, 1+ hour ago (37+ words) The impact of combining electrical and optical test in a single device. The post Challenges In Testing Photonics In Chips appeared first on Semiconductor Engineering. The impact of combining electrical and optical test in a single device....

4+ day, 2+ hour ago (734+ words) Deals, deals, deals; IC tariffs delay; chips for the Middle East; Deloitte's IC predictions; EU Chips Act; memory prices; issues in ramping advanced packaging; CXL 4.0 spec.; new university nano fab; AI legislation block. The Dutch government announced the suspension of its Nexperia intervention after "constructive" talks with Beijing. China urged the Dutch government to take "practical actions" to resolve the dispute over Nexperia, saying Dutch intervention and court rulings have created "chaos and turbulence" in the global semiconductor supply chain, reports Reuters. Financial releases this week: NVIDIA and'Soitec. Quick links to more news: Reports and Deals In-Depth Global New Technologies Security Automotive Research Education and Training Quantum Events and Further Reading More reporting this week: Issues In Ramping Advanced Packaging: Why traditional daisy chain approaches fall short. Jack Lewis, chief technologist at Modus Test, talks about how to obtain data…...

5+ day, 1+ hour ago (563+ words) Using virtual fabrication to assess edge placement error and pattern 18nm metal pitch successfully. At the N3 node, where metal pitch dimensions must be at or below 18 nm,1,2one of the main interconnect challenges is securing sufficient process margins for CD and edge placement error (EPE). SEMulator3Dvirtual fabrication, part of Semiverse Solutions, was used in a Design of Experiments (DOE) to evaluate EPE and demonstrate the ability to successfully pattern an advanced 18- and 16-nm metal pitch (MP) BEOL. Using a process model, we explored the impact of process variations and patterning sensitivities on EPE variability. The simulation identified significant process parameters and corresponding process windows that need to be controlled for successful EPE control. A self-aligned litho-etch litho-etch (SALELE) scheme with self-aligned blocks was proposed for an 18-nm MP BEOL process flow used at the N3 node. The advantage of this scheme is that no…...

5+ day, 1+ hour ago (147+ words) Standards like Universal Chiplet Interconnect Express (UCIe) are evolving rapidly, with aggressive targets for future versions. Customers are learning from current-generation designs while proposing incremental architecture changes. This raises a critical question: What does this mean for production testing? A large fraction of today's 2.5D products are processors, AI accelerators, and high-bandwidth memory (HBM). As architectures evolve toward 3D integration, test complexity will increase dramatically. Why? Without careful planning, these factors can extend time-to-market, a risk no one can afford. How can developers keep testing affordable and efficient? Here are key strategies: SLT remains a cornerstone of manufacturing test flows. As chiplet complexity grows, SLT ensures that the entire system functions as intended, bridging the gap between component-level and end-product validation. Discover how Amkor's advanced test services can help you achieve optimal quality and efficiency for chiplet-based designs....